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Si4320
AC Characteristics (continued)
Symbol
f ref
f res
Parameter
PLL reference frequency
PLL frequency resolution
Conditions/Notes
(Note 3)
Depends on selected bands
Min
8
2.5
Typ
10
Max
12
7.5
Units
MHz
kHz
t lock
t st, P
PLL lock time
PLL startup time
Frequency error < 1kHz after 10 MHz
step
With running crystal oscillator
20
250
μs
μs
C xl
t POR
t sx
Crystal load capacitance,
see crystal selection guide
Internal POR pulse width (Note 4)
Crystal oscillator startup time
Programmable in 0.5 pF steps, tolerance
+/- 10%
After V dd has reached 90% of final value
Crystal ESR < 100 Ohms (Note 5)
8.5
50
1
16
150
5
pF
ms
ms
Crystal oscillator must be enabled to
t PBt
Wake-up timer accuracy
ensure proper calibration at startup
+/-10
%
(Note 5)
t wake-up
C in, D
t r, f
Programmable wake-up time
Digital input capacitance
Digital output rise/fall time
15 pF pure capacitive load
1
5 · 10
2
10
11
ms
pF
ns
Note 3:
Note 4:
Note 5:
Using other than a 10 MHz crystal is not recommended because the crystal referred timing and frequency parameters will change
accordingly.
During this period, commands are not accepted by the chip. For detailed information see the Reset modes section.
The crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. Using low capacitance and low ESR
crystal is recommended. When designing the PCB layout keep the trace connecting to the crystal short to minimize stray
capacitance.
10
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